In-Place Parallel Super Scalar Samplesort (IPS⁴o)

Basically.

Intel processors can process something like 2 or 3 load/stores per clock cycle to L1 cache at full rate, no questions asked.

When you use AVX512 and do 512-bit loads/stores (64-byte), that's still only 2 or 3 per clock cycle. But if you use typical 64-bit registers, you're still only able to do 2 or 3 load/stores per cycle. Its not even memory latency here, its literally the execution port that's the holdup.

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Now I've never looked at AVX512 / AVX2 (256-bit) from the perspective of multithreaded / atomic access / memory order. But from a performance perspective, that load/store is the full 512-bit or 256-bit width and probably atomic.

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I'm assuming the 16-byte atomic compare-and-exchange instructions are NEON on ARM (128-bit width), and probably some AVX instruction I'm not aware of on Intel/AMD (256-bit).

EDIT: It seems like the 128-bit instruction on x86 is cmpxchg16b. 512-bit / 64-byte cache lines are the unit that the cache operates however. Intel has a TSX-NI (transactional memory) extension that operates over 64-bytes (making it possible to implement a cmpxchg64b, but over multiple instructions). Its not actually AVX512 or AVX2 related at all.